Follow us on Twitter
Browse patents:
Alternate imaging order for improved duplex throughput in a continuous print transfer printer
/ Xerox Corporation
Title: Alternate imaging order for improved duplex throughput in a continuous print transfer printer.Abstract: A method/printer prints images on an “A” side of a first sheet of media and on an “A” side of a second sheet of media in a single full transfer rotation of a drum. The method then prints images on the B side of the first sheet and on an A side of a third sheet in a single full transfer rotation of the drum. Similarly, the method prints images on the B side of the second sheet and on an A side of a fourth sheet in a single full transfer rotation of the drum. This method then prints images on the B side of the third sheet and the B side of the fourth sheet in a single full transfer rotation of the drum. ...
Browse recent USPTO Applicaton #: #
Inventors: ,
The Patent Description & Claims data below is from USPTO Patent Application , Alternate imaging order for improved duplex throughput in a continuous print transfer printer.
BACKGROUND
Embodiments herein generally relate to printing devices and more particularly to a printing device that modifies image creation order within a duplexing operation.
Competitive pressures demand the fastest possible printing speeds, while at the same time, prices must be held or lowered. Cost effective method and hardware solutions have been implemented in past products. The need for further improvement is always present, although elusive.
One advance included in some modern offset imaging devices, such as printers, MFPs, all-in-ones and the like, may be referred to as a multi-image duplexing printer capable of concurrently creating (jetting) two or more images or pages. With a multi-image duplexing printer, multiple images jetted onto an offset image receiving surface can be transferred to multiple sheets of media in a single transfer cycle. For example, marking material or ink, such as solid ink in a molten state, is jetted onto the image receiving surface, hereafter generally referred to as a drum, and each transfer rotation of the drum can transfer the multiple images to at least two sheets of media as the sheets pass through a transfix nip. Transfix is a term used to refer to image transfer to media from the offset image receiving surface by employing heat and/or pressure to fuse or fix the image to the media as the media and image pass through a transfer zone or nip. Transfer roller, pressure roller and transfix roller as used herein have the same meaning. Image refers to text and/or graphics created with an ink or marking material that is applied to one side of a media sheet. The terms media and paper may be used interchangeably and either term is intended to apply to any type of printable material. The surface receiving the jetted ink image prior to transfer to media is herein referred to as a drum or image receiving surface. The term drum herein encompasses any image receiving configuration with or without a surface coating, including a drum, band, belt or platen.
Conventional printing systems often provide the benefit of reduced paper consumption by enabling duplex printing (images on both sides of a sheet of media). Such duplexing operations are often accomplished by printing on one side of a sheet of media and then, rather than outputting the sheet from the printing device, directing the sheet of media through a duplex path. The duplex path reverses the orientation of the sheet of media with respect to the side being imaged (flips the sheet) and then reroutes the sheet through the imaging path to allow image transfer to the second side of the sheet. One issue associated with such duplexing operations is the time delay that occurs when the sheets are passed through the duplexing path.
One exemplary two-up, three sheet embodiment herein is a method that jets the “A” image for a first sheet of media and an “A” side for a second sheet of media in a single imaging cycle. The cycle for jetting or imaging on the receiving surface may require multiple passes or drum revolutions. After jetting the images, they are transferred to two sheets of media within one drum revolution. This transfer process continues for the subsequent sequence. In order to simplify the explanation, each sheet of media will be considered to have one first or “A” side and one second or “B” side. Further, to simplify this example, duplex printing is performed on only
however, as would be understood by those ordinarily skilled in the art, the process could be used for any number of sheets.
The method then jets an image for the B side of the first sheet and for an A side of a third sheet in a single imaging cycle. In the next imaging sequence, the image for a B side of the second sheet and a B side of the third sheet are imaged. Prints are created by transferring (transfixing) the images to media as each imaging cycle is completed.
An exemplary four sheet method concurrently prints the “A” side image of a first sheet of media and the “A” side image of a second sheet of media. The method then prints the B side of the first sheet and the A side of a third sheet. Similarly, the method prints the B side of the second sheet and the A side of a fourth sheet followed by imaging the B side of the third sheet and the B side of the fourth sheet.
A printing device embodiment herein includes a media sheet supply, a paper path positioned to transport the media sheets, a release surface or drum positioned to receive the media sheets from the paper path, and an ink jet print head positioned to jet the ink to form an image on the release surface of the drum. A processor is operatively connected to (directly or indirectly) the paper path, the drum and the printhead.
The processor controls the various operations involved in printing, for example, drum motion and printhead imaging for the A side image of a first sheet and the A side of a second sheet then the media path and transfix roller to transfer the images to the “A” side of a first and a second media sheet. The processor similarly controls printing operations to create the B side of the first sheet and an A side of a third sheet. The processor also controls printing operations to create the B side of the second sheet and the B side of the third.
In another printing device embodiment herein the processor controls drum motion and printhead imaging for an A side image of a first sheet and the A side of a second sheet then the media path and transfix roller to transfer the images to the “A” side of a first and a second media sheet. The processor similarly controls printing operations to create the B side of the first sheet and an A side of a third sheet. Then, the processor controls printing operations to create the B side of the second sheet and the A side of a fourth sheet. The processor then controls printing operations to create the B side of the third sheet and the B side of the fourth sheet.
These and other features are described in, or are apparent from, the following detailed description.
BRIEF DESCRIPTION OF THE DRAWINGS
Various exemplary embodiments of the systems and methods are described in detail below, with reference to the attached drawing figures, in which:
FIG. 1A is a block diagram of a printing device according t
FIG. 1B is a schematic diagram of a printing device according t
FIG. 2 is a schematic diagram of a printing device according t
FIG. 3 is a schematic diagram of a printing device according t
FIG. 4 is a schematic diagram of a printing device according t
FIG. 5 is a schematic diagram of a printing device according t
FIG. 6 is a schematic diagram of a printing device according t
FIG. 7 is a schematic diagram of a printing device according t
FIG. 8 is a schematic diagram of a printing device according t
FIG. 9 is a schematic diagram of a printing device according t
FIG. 10 is a schematic diagram of a printing device according t
FIG. 11 is a schematic diagram of a printing device according t
FIG. 12 is a schematic diagram of a device according t
FIG. 13 is a schematic diagram of a printing device according t
FIG. 14 is a flow diagram illustrating
FIG. 15 is a schematic diagram of a printing device according t
FIG. 16 is a schematic diagram of a printing device according t
FIG. 17 is a schematic diagram of a printing device according t
FIG. 18 is a flow diagram illustrating
FIG. 19 is a flow diagram illustrating a conventional duplex sequence in comparison to
You can also Monitor Keywords and Search for tracking patents relating to this Alternate imaging order for improved duplex throughput in a continuous print transfer printer patent application.
Browse recent
How KEYWORD MONITOR works... a FREE service from FreshPatents1.
(takes 30 seconds). 2.
to be monitored.
3. Each week you receive an email with patent applications related to your keywords.&& - Receive info on patent apps like Alternate imaging order for improved duplex throughput in a continuous print transfer printer or other areas of interest.###
Previous Patent Application:Next Patent Application:Industry Class:Thank you for viewing the Alternate imaging order for improved duplex throughput in a continuous print transfer printer patent info.- -
Results in 0.07439 seconds
categories:
###Data source: patent applications published in the public domain by the United States Patent and Trademark Office (USPTO). Information published here is for research/educational purposes only.
FreshPatents is not affiliated with the USPTO, assignee companies, inventors, law firms or other assignees. Patent applications, documents and images may contain trademarks of the respective companies/authors. FreshPatents is not responsible for the accuracy, validity or otherwise contents of these public document patent application filings. When possible a complete PDF is provided, however, in some cases the presented document/images is an abstract or sampling of the full patent application for display purposes.
-g2-0.002966.232.115.224
Browse patents:
Patent InfoApplication # US
A1Publish Date
06/21/2012 Document #
12/31/1969 USPTO Class
Other USPTO Classes
International Class
/ Drawings
Follow us on Twitter
Xerox CorporationBrowse recent Browse patents:
|alternate imaging order for improved duplex throughput in a continuous print transfer printer|A method/printer prints images on an “A” side of a first sheet of media and on an “A” side of a second sheet of media in a single full transfer rotation of a drum. The method then prints images on the B side of the first sheet and on an |Xerox-CorporationMemory device.
European Patent Application EP0415546
A memory for storing data in a computer system. Integrity of data transferred to or from a memory array is monitored by transferring two sets of EDC or ECC data corresponding to a longword of data between the memory array and two separate memory controllers. The probability of an undetected error is very low because the two sets of EDC or ECC data are compared to ensure that they match. The number of lines and pins used is minimized by multiplexing the EDC or ECC data with address signals and cycle type signals. The address and cycle type signals are placed on the time division multiplexed bidirectional lines at the beginning of a memory transfer cycle, and the EDC or ECC data is placed on these time division multiplexed lines at times when a longword of data is being transferred on a set of bidirectional data lines.
Inventors:
Bissett, Thomas D. (US)
Riegelhaupt, Norbert H. (US)
Berkson, Mitch (US)
Application Number:
Publication Date:
03/06/1991
Filing Date:
07/20/1990
Export Citation:
DIGITAL EQUIPMENT CORP (US)
International Classes:
G06F12/16; G06F11/10; G06F11/16; (IPC1-7): G06F11/10
European Classes:
G06F11/10M2D
View Patent Images:
&&&&&&PDF help
Domestic Patent References:
Foreign References:
4253147Memory unit with pipelined cycle of operations4689792Self test semiconductor memory with error correction capability
1. A memory for storing data in a computer system, wherein the computer system includes a memory controller means for writing or reading data during a memory transfer cycle, and a memory interface bus for coupling the memory to the memory controller means, wherein the memory interface bus includes a plurality of bidirectional data lines, a plurality of time division multiplexed bidirectional lines, and a cycle timing line for providing cycle timing signals to the memory, and wherein the memory comprises: : memory array means including a plurality of addressable storage locations, for storing data and ECC sequencer means, coupled to the cycle timing line, for generating a plurality of sequence timing signals in accordance with a clock signal and the
data buffer means, coupled to the plurality of bidirectional data lines, to the memory array means, and to the sequencer means, for transferring data between the bidirectional data lines and the memory array means, when enabled by the sequence timing signals during the m ; control buffer means, coupled to the plurality of time division multiplexed bidirectional lines, to the memory array, and to the sequencer means, for transferring address signals, provided on the time division multiplexed bidirectional lines by the memory controller means, from the time division multiplexed bidirectional lines to the memory array means, to access the addressable storage locations in the memory array means specified by the address signals, when enabled by sequence timing signals at the beginning of the m and for transferring ECC signals, between the time division multiplexed bidirectional lines and the memory array means, at times when data is transferred between the bidirectional data lines and the memory array means, when enabled by sequence timing signals after the beginning of the memory transfer cycle.
2. A memory for storing data in a computer system, wherein the computer system includes a memory controller means for writing or reading data during a memory transfer cycle, and a memory interface bus for coupling the memory to the memory controller means, wherein the memory interface bus includes a plurality of bidirectional data lines, a plurality of time division multiplexed bidirectional lines, and a cycle timing line for providing cycle timing signals to the memory, and wherein the memory comprises: : memory array means including a plurality of addressable storage locations, for storing data and ECC sequencer means, coupled to the cycle timing line, for generating a plurality of sequence timing signals in accordance with a clock signal and the
data buffer means, coupled to the plurality of bidirectional data lines, to the memory array means, and to the sequencer means, for transferring data between the bidirectional data lines and the memory array means, when enabled by the sequence timing signals during the m ; control buffer means, coupled to the plurality of time division multiplexed bidirectional lines, to the memory array, and to the sequencer means, for transferring cycle type signals, provided on the time division multiplexed bidirectional lines by the memory controller means, from the time division multiplexed bidirectional lines to the control buffer means, to enable reading or writing of data in accordance with the type of memory transfer cycle specified by the cycle type signals, when enabled by sequence timing signals at the beginning of the m and for transferring ECC signals, between the time division multiplexed bidirectional lines and the memory array means, at times when data is transferred between the bidirectional data lines and the memory array means, when enabled by sequence timing signals after the beginning of the memory transfer cycle.
3. A memory for storing data in a computer system, wherein the computer system includes a memory controller means for writing or reading data during a memory transfer cycle, and a memory interface bus for coupling the memory to the memory controller means, wherein the memory interface bus includes a plurality of bidirectional data lines, a plurality of time division multiplexed bidirectional lines, and a cycle timing line for providing cycle timing signals to the memory, and wherein the memory comprises: : memory array means including a plurality of addressable storage locations, for storing data and ECC sequencer means, coupled to the cycle timing line, for generating a plurality of sequence timing signals in accordance with a clock signal and the
data buffer means, coupled to the plurality of bidirectional data lines, to the memory array means, and to the sequencer means, for transferring data between the bidirectional data lines and the memory array means, when enabled by the sequence timing signals during the m ; control buffer means, coupled to the plurality of time division multiplexed bidirectional lines, to the memory array, and to the sequencer means, for transferring cycle type signals, provided on a first portion of the time division multiplexed bidirectional lines by the memory controller means, from the time division multiplexed bidirectional lines to the control buffer means, to enable reading or writing of data in accordance with the type of memory transfer cycle specified by the cycle type signals, when enabled by sequence timing signals at the beginning of the m ; for transferring address signals, provided on a second portion of the time division multiplexed bidirectional lines by the memory controller means, from the time division multiplexed bidirectional lines to the memory array means, to access the addressable storage locations in the memory array means specified by the address signals, when enabled by sequence timing signals at the beginning of the m and for transferring ECC signals, between the time division multiplexed bidirectional lines and the memory array means, at times when data is transferred between the bidirectional data lines and the memory array means, when enabled by sequence timing signals after the beginning of the memory transfer cycle.
Description:
The interrupt lines preferably contain one line for each of the interrupt levels available to I/O subsystem (modules 100, 110, 120, 100 min , 110 min and 120 min ). These lines are shared by cross-links 90, 95, 90 min and 95 min .The coded error lines preferably include codes for synchronizing a console "HALT" request for both zones, one for synchronizing a CPU error for both zones, one for indicating the occurrence of a CPU/memory failure to the other zone, one for synchronizing DMA error for both zones, and one for indicating clock phase error. The error lines from each zone 11 or 11 min are inputs to an OR gate, such as OR gate 1990 for zone 11 or OR gate 1990 min for zone 11 min . The output at each OR gate provides an input to the cross-links of the other zone.The fault tolerant processing system 10 is designed to continue operating as a dual rail system despite transient faults. The I/O subsystem (modules 100, 110, 120, 100 min , 110 min , 120 min ) can also experience transient errors or faults and continue to operate. In the preferred embodiment, an error detected by firewall comparison circuit 1840 will cause a synchronized error report to be made through pathway 25 for CPU directed operations. Hardware in CPU 30 and 30 min will cause a synchronized soft reset through pathway 25 and will retry the faulted operation. For DMA directed operations, the same error detection results in synchronous interrupts through pathway 25, and software in CPUs 40, 50, 40 min and 50 min will restart the DMA operation.Certain transient errors are not immediately recoverable to allow continued operation in a full-duplex, synchronized fashion. For example, a control error in memory module 60 can result in unknown data in memory module 60. In this situation, the CPUs and memory elements can no longer function reliably as part of a fail safe system so they are removed. Memory array 60 must then undergo a memory resync before the CPUs and memory elements can rejoin the system. The CPU/memory fault code of the coded error lines in pathway 25 indicates to CPU 30 min that the CPUs and memory elements of CPU 30 have been faulted.The control lines, which represent a combination of cycle type, error type, and ready conditions, provide the handshaking between CPU modules (30 and 30 min ) and the I/O modules. Cycle type, as explained above, defines the type of bus operation being performed: CPU I/O read, DMA transfer, DMA setup, or interrupt vector request. Error type defines either a firewall miscompare or a CRC error. "Ready" messages are sent between the CPU and I/O modules to indicate the completion of requested operations.The serial cross-link includes two sets of two lines to provide a serial data transfer for a status read, loopback, and data transfer.The clock signals exchanged are the phase locked clock signals CLKC H and CLKC min H (delayed).Figs. 20A-D show block diagrams of the elements of CPU modules 30 and 30 min and I/O modules 100 and 100 min through which data passes during the different operations. Each of those elements has each been described previously.Fig. 20A shows the data pathways for a typical CPU I/O read operation of data from an I/O module 100, such as a CPU I/O register read operation of register data from shaved memory controller
min ). Such an operation will be referred to as a read of local data, to distinguish it from a DMA read of data from local memory 1060, which usually contains data from an internal device controller. The local data are presumed to be stored in local RAM
min ) for transfer through shared memory controller
min ). For one path, the data pass through firewall 1000, module interconnect 130, to cross-link 90.As seen in Fig. 12, cross-link 90 delays the data from firewall 1000 to memory controller 70 so that the data to cross-link 90 min may be presented to memory controller 70 at the same time the data are presented to memory controller 70, thus allowing processing systems 20 and 20 min to remain synchronized. The data then proceed out of memory controllers 70 and 70 min into CPUs 40 and 40 min by way of internal busses 46 and 46 min .A similar path is taken for reading data into CPUs 50 and 50 min . Data from the shared memory controller 1050 proceeds through firewall 1010 and into cross-link 95. At that time, the data are routed both to cross-link 95 min and through a delay unit inside cross-link 95.CPU I/O read operations may also be performed for data received from the I/O devices of processing system 20 min via a shared memory controller 1050 min and local RAM in I/O device 100 min .Although I/O modules 100, 110, and 120 are similar and correspond to I/O modules 100 min , 110 min , and 120 min , respectively, the corresponding I/O modules are not in lockstep synchronization. Using memory controller 1050 min and local RAM 1060 min for CPU I/O read, the data would first go to cross-links 90 min and 95 min . The remaining data path is equivalent to the path from memory controller 1050. The data travel from the cross-links 90 min and 95 min up through memory controllers 70 min and 75 min and finally to CPUs 40 min and 50 min , respectively. Simultaneously, the data travel across to cross-links 90 and 95, respectively, and then, without passing through a delay element, the data continue up to CPUs 40 and 50, respectively.Fig. 20B shows a CPU I/O write operation of local data. Such local data are transferred from the CPUs 40, 50, 40 min and 50 min to an I/O module, such as I/O module 100. An example of such an operation is a write to a register in shared memory controllers 1050. The data transferred by CPU 40 proceed along the same path but in a direction opposite to that of the data during the CPU I/O read. Specifically, such data pass through bus 46, memory controller 70, various latches (to permit synchronization), firewall 1000, and memory controller 1050. Data from CPU 50 min also follow the path of the CPU I/O reads in a reverse direction. Specifically, such data pass through bus 56 min , memory controller 75 min , cross-link 95 min , cross-link 95, and into firewall 1010.As indicated above, firewalls 1000 and 1010 check the data during I/O write operations to check for errors prior to storage.When writes are performed to an I/O module in the other zone, a similar operation is performed. However, the data from CPUs 50 and 40 min are used instead of CPUs 50 min and 40.The data from CPUs 50 and 40 min are transmitted through symmetrical paths to shared memory controller 1050 min . The data from CPUs 50 and 40 min are compared by firewalls 1000 min and 1010 min . The reason different CPU pairs are used to service I/O write data is to allow checking of all data paths during normal use in a full duplex system. Interrail checks for each zone were previously performed at memory controllers 70, 75, 70 min and 75 min .Fig. 20C shows the data paths for DMA read operations. The data from memory array 600 pass simultaneously into memory controllers 70 and 75 and then to cross-links 90 and 95. Cross-link 90 delays the data transmitted to firewall 1000 so that the data from cross-links 90 and 95 reach firewalls 1000 and 1010 at substantially the same time.Similar to the CPU I/O write operation, there are four copies of data of data to the various cross-links. At the firewall, only two copies are received. A different pair of data are used when performing reads to zone 11. The data paths for the DMA write operation are shown in Fig. 20D and are similar to those for a CPU I/O read. Specifically, data from shared memory controller 1050 min proceed through firewall 1000 min , cross-link 90 min (with a delay), memory controller 70 min , and into memory array 600 min . Simultaneously, the data pass through firewall 1010 min , cross-link 95 min (with a delay), and memory controller 75 min , at which time it is compared with the data from memory controller 70 min during an interrail error check.As with the CPU I/O read, the data in a DMA write operation may alternatively be brought up through shared memory controller 1050 in an equivalent operation.The data out of cross-link 90 min also pass through cross-link 90 and memory controller 70 and into memory array 600. The data from cross-link 95 min pass through cross-link 95 and memory controller 75, at which time they are compared with the data from memory controller 70 min during a simultaneous interrail check.The data path for a memory resynchronization (resync) operation is shown in Fig. 20E. In this operation the contents of both memory arrays 60 and 60 min must be set equal to each other. In memory resync, data from memory array 600 min pass through memory controllers 70 min and 75 min under DMA control, then through cross-links 90 min and 95 min , respectively. The data then enters cross-links 90 and 95 and memory controllers 70 and 75, respectively, before being stored in memory array 600. 2. ResetsThe preceding discussions of system 10 have made reference to many different needs for resets. In certain instances not discussed, resets are used for standard functions, such as when power is initially applied to system 10. Most systems have a single reset which always sets the processor back to some predetermined or initial state, and thus disrupts the processors' instruction flow. Unlike most other systems, however, resets in system 10 do not affect the flow of instruction execution by CPUs 40, 40 min , 50 and 50 min unless absolutely necessary. In addition, resets in system 10 affect only those portions that need to be reset to restore normal operation.Another aspect of the resets in system 10 is their containment. One of the prime considerations in a fault tolerant system is that no function should be allowed to stop the system from operating should that function fail. For this reason, no single reset in system 10 controls elements of both zones 11 and 11 min without direct cooperation between zones 11 and 11 min . Thus, in full duplex mode of operation, all resets in zone 11 will be independent of resets in zone 11 min . When system 10 is in master/slave mode, however, the slave zone uses the resets of the master zone. In addition, no reset in system 10 affects the contents of memory chips. Thus neither cache memory 42 and 52, scratch pad memory 45 and 55 nor memory module 60 lose any data due to a reset.There are preferably three classes of resets in system 10; "clock reset," "hard reset," and "soft reset." A clock reset realigns all the clock phase generators in a zone. A clock reset in zone 11 will also initialize CPUs 40 and 50 and memory module 60. A clock reset does not affect the module interconnects 130 and 132 except to realign the clock phase generators on those modules. Even when system 10 is in master/slave mode, a clock reset in the slave zone will not disturb data transfers from the master zone to the slave zone module interconnect. A clock reset in zone 11 min , however, will initialize the corresponding elements in zone 11 min .In general, a hard reset returns all state devices and registers to some predetermined or initial state. A soft reset only returns state engines and temporary storage registers to their predetermined or initial state. The state engine in a module is the circuitry that defines the state of that module. Registers containing error information and configuration data will not be affected by a soft reset. Additionally, system 10 will selectively apply both hard resets and soft resets at the same time to reset only those elements that need to be reinitialized in order to continue processing.The hard resets clear system 10 and, as in conventional systems, return system 10 to a known configuration. Hard resets are used after power is applied, when zones are to be synchronized, or to initialize or disable an I/O module. In system 10 there are preferably four hard resets: "power up reset," "CPU hard reset," "module reset," and "device reset." Hard resets can be further broken down into local and system hard resets. A local hard reset only affects logic that responds when the CPU is in the slave mode. A system hard reset is limited to the logic that is connected to cross-link cables 25 and module interconnects 130 and 132.The power up reset is used to initialize zones 11 and 11 min immediately after power is supplied. The power up reset forces an automatic reset to all parts of the zone. A power up reset is never connected between the zones of system 11 because each zone has its own power supply and will thus experience different length "power-on" events. The power up reset is implemented by applying all hard resets and a clock reset to zone 11 or 11 min .The CPU hard reset is used for diagnostic purposes in order to return a CPU module to a known state. The CPU hard reset clears all information in the CPUs, memory controllers, and memory module status registers in the affected zone. Although the cache memories and memory modules are disabled, the contents of the scratch pad RAMs 45 and 55 and of the memory module 60 are not changed. In addition, unlike the power up reset, the CPU hard reset does not modify the zone identification of the cross-links nor the clock mastership. The CPU hard reset is the sum of all local hard resets that can be applied to a CPU module and a clock reset.The module hard reset is used to set the I/O modules to a known state, such as during bootstrapping, and is also used to remove a faulting I/O module from the system. The I/O module hard reset clears everything on the I/O module, leaves the firewalls in a diagnostic mode, and disables the drivers.A device reset is used to reset I/O devices connected to the I/O modules. The resets are device dependent and are provided by the I/O module to which the device is connected.The other class of resets is soft resets. As explained above, soft resets clear the state engines and temporary registers in system 10 but they do not change configuration information, such as the mode bits in the cross-links. In addition, soft resets also clear the error handling mechanisms in the modules, but they do not change error registers such as system error register 898 and system fault address register 865.Soft resets are targeted so that only the necessary portions of the system are reset. For example, if module interconnect 130 needs to be reset, CPU 40 is not reset nor are the devices connected to I/O module 100.There are three unique aspects of soft resets. One is that each zone is responsible for generating its own reset. Faulty error or reset logic in one zone is thus prevented from causing resets in the non-faulted zone.The second aspect is that the soft reset does not disrupt the sequence of instruction execution. CPUs 40, 40 min , 50, 50 min are reset on a combined clock and hard reset only. Additionally memory controllers 70, 75, 70 min and 75 min have those state engines and registers necessary to service CPU instructions attached to hard reset. Thus the soft reset is transparent to software execution.The third aspect is that the range of a soft reset, that is the number of elements in system 10 that is affected by a soft reset, is dependent upon the mode of system 10 and the original reset request. In full duplex mode, the soft reset request originating in CPU module 30 will issue a soft reset to all elements of CPU module 30 as well as all firewalls 1000 and 1010 attached to module interconnect 130 and 132. Thus all modules serviced by module interconnect 130 and 132 will have their state engines and temporary registers reset. This will clear the system pipeline of any problem caused by a transient error. Since system 10 is in duplex mode, zone 11 min will be doing everything that zone 11 is. Thus CPU module 30 min will, at the same time as CPU module 30, issue a soft reset request. The soft reset in zone 11 min will have the same effect as the soft reset in zone 11.When system 10 is in a master/slave mode, however, with CPU module 30 min in the slave mode, a soft reset request originating in CPU module 30 will, as expected, issue a soft reset to all elements of CPU module 30 as well as all firewalls 1000 and 1010 attached to module interconnects 130 and 132. Additionally, the soft reset request will be forwarded to CPU module 30 min via cross-links 90 and 90 min , cross-link cables 25, and cross-links 90 min and 95 min . Parts of module interconnects 130 min and 132 min will receive the soft reset. In this same configuration, a soft reset request originating from CPU module 30 min will only reset memory controllers 70 min and 75 min and portions of cross-links 90 min and 95 min .Soft resets include "CPU soft resets" and "system soft resets." A CPU soft reset is a soft reset that affects the state engines on the CPU module that originated the request. A system soft reset is a soft reset over the module interconnect and those elements directly attached to it. A CPU module can always request a CPU soft reset. A system soft reset can only be requested if the cross-link of the requesting CPU is in duplex mode, master/slave mode, or off mode. A cross-link in the slave mode will take a system soft reset from the other zone and generate a system soft reset to its own module interconnects.CPU soft resets clear the CPU pipeline following an error condition. The CPU pipeline includes memory interconnects 80 and 82, latches (not shown) in memory controllers 70 and 75, DMA engine 800, and cross-links 90 and 95. The CPU soft reset can also occur following a DMA or I/O time-out. A DMA or I/O time-out occurs when the I/O device does not respond within a specified time period to a DMA or an I/O request.Fig. 21 shows the reset lines from the CPU modules 30 and 30 min to the I/O modules 100, 110, 100 min , and 110 min and to the memory modules 60 and 60 min . The CPU module 30 receives a DC OK signal indicating when the power supply has settled. It is this signal which initializes the power-up reset. CPU module 30 min receives a similar signal from its power supply.One system hard reset line is sent to each I/O module, and one system soft reset is sent to every three I/O modules. The reason that single hard reset is needed for each module is because the system hard reset line are used to remove individual I/O modules from system 10. The limitation of three I/O modules for each system soft reset is merely a loading consideration. In addition, one clock reset line is sent for every I/O module and memory module. The reason for using a single line per module is to control the skew by controlling the load.Fig. 22 shows the elements of CPU module 30 which relate to resets. CPUs 40 and 50 contain clock generators 2210 and 2211, respectively. Memory controllers 70 and 75 contain clock generators 2220 and 2221, respectively, and cross-links 90 and 95 contain clock generators 2260 and 2261, respectively. The clock generators divide down the system clock signals for use by the individual modules.Memory controller 70 contains reset control circuitry 2230 and a soft reset request register 2235. Memory controller 75 contains reset control circuitry 2231 and a soft reset request register 2236.Cross-link 90 contains both a local reset generator 2240 and a system reset generator 2250. Cross-link 95 contains a local reset generator 2241 and a system reset generator 2251. The "local" portion of a cross-link is that portion of the cross-link which remains with the CPU module when that cross link is in the slave mode and therefore includes the serial registers and some of the parallel registers. The "system" portion of a cross-link is that portion of the cross-link that is needed for access to module interconnects 130 and 132 (or 130 min and 132 min ) and cross-link cables 25.The local reset generators 2240 and 2241 generate resets for CPU module 30 by sending hard and soft reset signals to the local reset control circuits 2245 and 2246 of cross-links 90 and 95, respectively, and to the reset control circuits 2230 and 2231 of memory controller 70 and 75, respectively. Local cross-link reset control circuits 2245 and 2246 respond to the soft reset signals by resetting their state engines, the latches storing data to be transferred, and their error registers. Those circuits respond to the hard reset signals by taking the same actions as are taken for the soft resets, and by also resetting the error registers and the configuration registers. Reset control circuits 2230 and 2231 respond to hard and soft reset signals in a similar manner.In addition, the local reset generator 2240 sends clock reset signals to the I/O modules 100, 110 and 120 via module interconnects 130 and 132. The I/O modules 100, 110, and 120 use the clock reset signals to reset their clocks in the manner described below. Soft reset request registers 2235 and 2236 send soft request signals to local reset generators 2240 and 2241, respectively.System reset generators 2250 and 2251 of cross-links 90 and 95, respectively, send system hard reset signals and system soft reset signals to I/O modules 100, 110, and 120 via module interconnects 130 and 132, respectively. I/O modules 100, 110, and 120 respond to the soft reset signals by resetting all registers that are dependent on CPU data or commands. Those modules respond to the hard reset signals by resetting the same register as soft resets do, and by also resetting any configuration registers.In addition, the system reset generators 2250 and 2251 also send the system soft and system hard reset signals to the system reset control circuit 2255 and 2256 of each cross-link. System reset control circuit 2255 and 2256 respond to the system soft reset signals and to the system hard reset signals in a manner similar to the response of the local reset control circuits to the local soft and local hard reset signals.Memory controllers 70 and 75 cause cross-links 90 and 95, respectively, to generate the soft resets when CPUs 40 and 50, respectively, write the appropriate codes into soft reset request registers 2235 and 2236, respectively. Soft reset request registers 2235 and 2236 send soft reset request signals to local reset generators 2240 and 2241, respectively. The coded error signal is sent from memory controller 70 to local reset generators 2240 and 2241.System soft resets are sent between zones along the same data paths data and control signals are sent. Thus, the same philosophy of equalizing delays is used for resets as for data and addresses, and resets reach all of the elements in both zones at approximately the same time.Hard resets are generated by CPUs 40 and 50 writing the appropriate code into the local hard reset registers 2243 or by the request for a power up reset caused by the DC OK signal.Synchronization circuit 2270 in cross-link 90 includes appropriate delay elements to ensure that the DC OK signal goes to all of the local and reset generators , 2241 and 2251 at the same time.In fact, synchronization of resets is very important in system 10. That is why the reset signals originate in the cross-links. In that way, the resets can be sent to arrive at different modules and elements in the modules approximately synchronously.With the understanding of the structure in Figs. 21 and 22, the execution of the different hard resets can be better understood. The power up reset generates both a system hard reset, a local hard reset and a clock reset. Generally, cross-links 90, 95, 90 min and 95 min are initially in both the cross-link off and resync off modes, and with both zones asserting clock mastership.The CPU/MEM fault reset is automatically activated whenever memory controllers 70, 75, 70 min and 75 min detect a CPU/MEM fault. The coded error logic is sent from error logic 2237 and 2238 to both cross-links 90 and 95. The CPU module which generated the fault is then removed from system 10 by setting its cross-link to the slave state and by setting the cross-link in the other CPU module to the master state. The non-faulting CPU module will not experience a reset, however. Instead, it will be notified of the fault in the other module through a code in a serial cross-link error register (not shown). The CPU/MEM fault reset consists of a clock reset to the zone with the failing CPU module and a local soft reset to that module.A resync reset is essentially a system soft reset with a local hard reset and a clock reset. The resync reset is used to bring two zones into lockstep synchronization. If, after a period in which zones 11 and 11 min were not synchronized, the contents of the memory modules 60 and 60 min including the stored states of the CPU registers, are set equal to each other, the resync reset is used to bring the zones into a compatible configuration so they can restart in a duplex mode.The resync reset is essentially a CPU hard reset and a clock reset. The resync reset is activated by software writing the resync reset address into one of the parallel cross-link registers. At that time, one zone should be in the cross-link master/resync master mode and the other in the cross-link slave/resync slave mode. A simultaneous reset will then be performed on both the zones which, among other things, will set all four cross-links into the duplex mode. Since the resync reset is not a system soft reset, the I/O modules do not receive reset.The preferred embodiment of system 10 also ensures that clock reset signals do not reset conforming clocks, only non-conforming clocks. The reason for this is that whenever a clock is reset, it alters the timing of the clocks which in turn affects the operation of the modules with such clocks. If the module was performing correctly and its clock was in the proper phase, then altering its operation would be both unnecessary and wasteful.Fig. 23 shows a preferred embodiment of circuitry which will ensure that only nonconforming clocks are reset. The circuitry shown in Fig. 23 preferably resides in the clock generators , , 2260, and 2261 of the corresponding modules shown in Fig. 22.In the preferred embodiment, the different clock generators , , 2260, and 2261 include a rising edge detector 2300 and a phase generator 2310. The rising edge detector 2300 receives the clock reset signals from the cross-links 90 and 95 and generates a pulse of known duration concurrent with the rising edge of the clock reset signal. That pulse is in an input to the phase generator 2310 as are the internal clock signals for the particular module. The internal clock signals for that module are clock signals which are derived from the system clock signals that have been distributed from oscillator systems 200 and 200 min .Phase generator 2310 is preferably a divide-down circuit which forms different phases for the clock signals. Other designs for phase generator 2310, such as recirculating shift registers, can also be used.Preferably, the rising edge pulse from rising edge detector 2300 causes phase generator 2310 to output a preselected phase. Thus, for example, if phase generator 2310 were a divide-down circuit with several stages, the clock reset rising edge pulse could be a set input to the stage which generates the preselected phase and a reset input to all other stages. If phase generator 2310 were already generating that phase, then the presence of the synchronized clock reset signal would be essentially transparent.The resets thus organized are designed to provide the minimal disruption to the normal execution of system 10, and only cause the drastic action of interrupting the normal sequences of instruction execution when such drastic action is required. This is particularly important in a dual or multiple zone environment because of the problems of resynchronization which conventional resets cause. Thus, it is preferable to minimize the number of hard resets, as is done in system 10.It will be apparent to those skilled in the art that various modifications and variations can be made in the memory of the present invention without departing from teh scope or spirit of the invention. Thus, it is intended that the present invention cover the modifications and variations or this invention provided they come within the scope ot the appended claims and their equivalents.
& 2004-. All rights reserved.}