Glitch-Free Frequency Shifting | Silicon Labs
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Glitch-Free Frequency Shifting Simplifies Timing Design in Consumer Applications
Clock circuitry plays a valuable role in mitigating power and
design challenges in consumer electronics such as audio, video, computing or any application that requires multiple frequencies.
This in-depth Silicon Labs white paper focuses on how to simplify your timing design using glitch-free frequency shifting to address low power design challenges, as well as the complexity of generating a wide range of frequencies.
Simply fill out the form to get immediate access to this tutorial!Special pages
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Powered by&1`timescale&1ns/10ps&2module&clk_switch&(&3&&//&Outputs&4&&&&out_clk,&&&&5&&//&Inputs&&&6&&&&clk_a,&7&&&&clk_b,&8&&&&select&&&&);&&&9&&&input&clk_a;&&10&&&input&clk_b;&&11&&&input&&&12&&&output&out_&13&&&reg&out_14&&&always&@&(select&or&clk_a&or&clk_b)15&&&begin&&&16&&&&&&&if&select&==&1)&17&&&&&&&&&&out_clk&&=&clk_a;&&&18&&&&&&&else&&&&&&19&&&&&&&&&&out_clk&&=&clk_b;20&&&&&&&end21endmodule&Glitch free safe clock switch implementation
The logic is little complex than the simple clock switch, the clock switching will not happen immediately after switching the select signal. This circuit allows both clock settle down and switches the new clock to the circuit. It eliminates glitch or spikes in the clock signal. The safe clock switch circuit is implemented as in the following diagram. Safe Clock switch circuit
Following figure shows the simulation of glitch free safe clock switch. For both implementations same test bench is used. Code for the test bench is available at end of the article.
Above circuit works well with related and unrelated clock. Related clocks means both clocks come from the same clock source (they are in phase) un-related clocks (they are not in the phase) are not come from the same clock source. In this implementation the select signal registered it makes sure that the there will not be any change in the output while both clocks are high. First stage flip-flops remove the meta-stability problem. Verilog implementation for glitch free clock switch.&&1`timescale&1ns/100ps&2module&clk_switch&(&3&&&//&Outputs&4&&&out_clk,&5&&&//&Inputs&6&&&clk_a,&clk_b,&select&7&&&);&8&9&&&input&clk_a;10&&&input&clk_b;11&&&input&1213&&&output&out_14wire&&&out_1516reg&q1,q2,q3,q4;17wire&or_one,&or_two,or_three,or_1819always&@&(posedge&clk_a)20begin21&&&&if&(clk_a&==&1'b1)22&&&&begin23&&&&&&&q1&&=&q4;24&&&&&&&q3&&=&or_25&&&&end26end2728always&@&(posedge&clk_b)29begin30&&&&if&(clk_b&==&1'b1)31&&&&begin32&&&&&&&&q2&&=&q3;33&&&&&&&&q4&&=&or_34&&&&end35end3637assign&or_one&&&=&(!q1)&|&(!select);38assign&or_two&&&=&(!q2)&|&(select);39assign&or_three&=&(q3)&&|&(clk_a);40assign&or_four&&=&(q4)&&|&(clk_b);4142assign&out_clk&&=&or_three&&&or_4344endmodule&&&&&&&&&&&&&&&&&&&&&&&&& &TestBench&1`timescale&1ns/10ps&2&3module&tb_clk_&4&5&&&reg&&clk_a;&6&&&reg&&clk_b;&7&&&wire&out_&8&9&&&reg&1011&&&initial12&&&&&begin13&&&&&&&&select&&=&1'b0;14&&&&&&&&clk_a&&&&=&1'b1;15&&&&&&&&clk_b&&&&=&1'b1;16&&&&&&&&#87.217&&&&&&&&select&&=&1'b1;18&&&&&&&&#81.919&&&&&&&&select&&=&1'd0;20&&&&&&&&#5021&&&&&&&&$22&&&&&end2324&&&always&#5.7&&&clk_a&=&~clk_a;25&&&always&#2.5&&&clk_b&=&~clk_b;2627clk_switch&ins1&(28&&&.clk_a(clk_b),29&&&.clk_b(clk_a),30&&&.select(select),31&&&.out_clk(out_clk)32&&&);33endmodule &&}