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n-well是什么意思
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n-well是什么意思 n-well在线翻译 n-well什么意思 n-well的意思 n-well的翻译 n-well的解释 n-well的发音 n-well的同义词 n-well的反义词 n-well的例句
n-welln-well 双语例句1. The CMOS mixed signal sensor IC of compatible photo quadrants array and magnetic linear array are designed and fabricated in 0.6μm double metal double poly standard CMOS process. A 4×4 array of P＋/N-well/P-substrate photodiode and the 4×1 linear array of sector MAGFETs are designed. The pixel size of P＋/N-well/P-substrate photodiode is 100μam×100μm.&&&&本论文设计的光敏象限阵列和磁敏线阵列分别由4×4的有源双重结光电管阵列和4×1有源双向扇形MAGFET阵列组成，双重结光电管的面积为100μm×100μm，共源极双向扇形MAGFET的沟道半径为48μm，源极半径为10μm，源极展角为90°。2. CMSC 0.6μm 2 ploy n-well CMOS mixture signal model and Cadence Spectra tool were used for simulation. Simulation results showed that the output voltage varied lower than 1.6mV 6.2×l0^(-6/℃ and 0.13mV with a temperature range of -50℃ to 150℃ and the supply voltage ranged from 4.5V to 5.5V respectively.&&&&使用CSMC标准0.6μm双层多晶硅n-well CMOS工艺混频信号模型，利用Cadence的Spectre工具对其仿真，结果显示，当温度和电源电压变化范围为－50~150℃和4.5~5.5V时，输出基准电压变化小于1.6mV6.2×10^(-6/℃和0.13mV；低频电源抑制比达到75 dB。3. Always put a Guard Ring around the N-well and P-well.&&&&在 N 阱和 P 阱作保护环。4. n-well的解释4. The bipolar device comprises at least an N-well for providing a high resistance and a P material to be used as a collector thereof for further providing a high resistance.&&&&此双载流子装置包括至少一N型阱以及一P 材料。N型阱用以提供较高的电阻，而P 材料则作为一集电极，以提供一高电阻。5. The kind of bandgap voltage reference and driving circuit based on standard N-well CMOS process is given.&&&&基于标准N阱CMOS工艺设计了一种带隙基准电压产生及输出驱动转换电路。6. This low-pass filter was implemented with 1.2 μm 2P2M N-well CMOS process.&&&&该低通滤波器采用1.2μm的2P2M的N-阱CMOS工艺实现。7. Based on a method of temperature compensation, a novel super performance CMOS current reference circuit is presented. It is realized using the 0.35μm N-well CMOS process.&&&&基于温度补偿的方法设计了一种高性能的CMOS基准电流源电路，该电路采用0.35mm N阱 CMOS工艺实现。8. The chip is signed off successfully with a triple-mental 0.5μm one-poly N-well BiCMOS technology.&&&&芯片采用0.5μm的P衬N阱数模混合1P3M BiCMOS工艺流片。9. 9. Comparing with current technology, the provided circuit eliminates complicated detecting circuit, and the NMOS transistor and PMOS transistor can be made by using standard procedure but not complicated N-well procedure.&&&&本发明所述电路相对现有技术，省去了复杂的检测电路，本发明的NMOS和PMOS可以采用标准工艺，而不是复杂的N阱工艺。10. This paper describes the n-well CMOS/BIPOLAR compatible process.&&&&本文介绍n阱CMOS与BIPOlAR集成电路兼容工艺。11. Un-grid photodiode has lower dark current and larger photosensitive dynamic range, the dynamic range of P_ +/N-well/P-sub photodiode structure can be 139.8 dB when operating in reset frequency adjustment double scanning mode.&&&&&&非网格状光敏管结构具有较低的暗电流和较大的感光动态范围，其中P+/N阱/P衬底光敏管结构的传感单元在变频两次扫描的工作方式下的感光动态范围可达139.8dB。12. When the reset signal frequency is adjusted according to illumination intensity, the total dynamic range of the P~+/N-well/P-sub sensor can be increased to 139.8 dB. With P~+/N-well/P-sub structure photodiodes, performance of pixel is improved.&&&&&&通过改变复位信号频率，将P+/N-well/P-sub结构像素的感光动态范围提高到139.8dB，改善了有源像素的感光性能。13. Arranging the cell array in a N-well decreases the soft error rate.&&&&&&做在N阱内的单元阵列在抗α软失效方面有很大的好处。14. 14. The received signal strength indicator (RSSI) in a CMOS limiting/logarithmic amplifier, which is proposed for optical receiver at bit rate of 155 Mbit/s, is designed and realized in a 0.6 μ m double-poly n-well CMOS process.&&&&&&介绍了一种应用于光接收机系统、速率可达155Mbit/s的CMOS限幅/对数放大器的接收信号强度指示器（RSSI）。电路采用0.6μm双多晶硅N阱CMOS工艺设计并实现。15. An n-well CMOS and n-channel SCCD compatible IC process is described in the pa-per.&&&&&&本文介绍并讨论了一种n阱CMOS与n沟SCCD兼容的集成电路工艺。16. 16. An n-Well CMOS and n-Type Surface-Channel CCD Compatible IC Process&&&&&&n阱CMOS与n型表沟CCD兼容的集成电路工艺17. Latent damage in n-well diffused resistor under ESD stress&&&&&&ESD应力下n阱扩散电阻的潜在损伤18. The analysis in linear region of n-well LDMOS voltage - current characteristic&&&&&&n阱LDMOS伏安特性线性区的分析19. Moreover, the improved double delta sampling circuit is used to not only suppress fixed pattern noise, clock feedthrough noise, channel charge injection but also common mode noise. An experimental 1 x 128 readout chip has been designed and fabricated by using 0.35 μm 2P4M N-well CMOS technology. The measurement results of the fabricated readout chip under 298K and 3.3 V supply voltage have successfully verified both readout function and performance. The size of the chip is 7.4mmx1.6mm.&&&&&&改良后的双重三角取样电路除了可以减少固定样式杂讯、时脉回馈杂讯、通道电荷注入和共模杂讯，还可以改善线性度和增加输出电压的摆幅。1 x 128读出晶片使用0.35 μm 2P4M N-well互补式金氧半技术设计并完成晶片研制，在298K温度下及3.3 V工作电压，其量测结果成功验证了读出晶片的效能。20. The received signal strength indicator (RSSI) in a CMOS limiting / logarithmic amplifier, which is proposed for optical receiver at bit rate of 155 Mbit / s, is designed and realized in a 0.6 μ m double-poly n-well CMOS process.&&&&&&介绍了一种应用于光接收机系统、速率可达155Mbit/s的CMOS限幅/对数放大器的接收信号强度指示器（RSSI）。电路采用0.6μm双多晶硅N阱CMOS工艺设计并实现。n-well是什么意思,n-well在线翻译,n-well什么意思,n-well的意思,n-well的翻译,n-well的解释,n-well的发音,n-well的同义词,n-well的反义词,n-well的例句,n-well的相关词组,n-well意思是什么,n-well怎么翻译,单词n-well是什么意思常用英语教材考试英语单词大全 (7本教材)
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良好的研究
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